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PALCE610H-25PC - Lattice Semiconductor - USE GAL DEVICES FOR NEW DESIGNS

PALCE610H-25PC - Lattice Semiconductor - USE GAL DEVICES FOR NEW DESIGNS

  • PALCE610H-25PC - Lattice Semiconductor - USE GAL DEVICES FOR NEW DESIGNS
PALCE610H-25PC - Lattice Semiconductor - USE GAL DEVICES FOR NEW DESIGNS
Product Details:
Place of Origin: PHILIPPINE
Brand Name: Lattice Semiconductor
Certification: Leaded version
Model Number: PALCE610H-25PC
Payment & Shipping Terms:
Minimum Order Quantity: 5 PCS
Price: Contace sales group 1
Packaging Details: Standard Packaging
Delivery Time: 2-3 days
Payment Terms: T/T in advance, Paypal, Western Union
Supply Ability: 5000
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Detailed Product Description
High Light:

programmable ic chips

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integrated circuit chips

Quick Detail:

 

USE GAL DEVICES FOR NEW DESIGNS

 

 

Description:

 

The PALCE610 is a general purpose PAL device and is functionary and fuse map equivalent to the EP610. It can accommodate logic functions with up to 20 inputs and 16 outputs. There are 16 I/O macrocells that can be indrviduary configured to the user’s specifications. The macrocells can be configured as either registered or combinatorial. The registers can be configured as D.T.J-K. or S-R filp-flops.

The PALCE610 uses the familiar sum-of-productors logic with programmable-AND and fixed-OR structure. Eight product terms are brought to each macrocell toprovide logic implementations.

The PALCE610 is manufactured using advanced CMOS EE technology providing low power consumption. Moreover, it is a high-speed device having a worst-case tpd of 15ns .Space-saving24-pin SKINNYDIP and 28-pin PLCC packages are offered.

This device can be quickly erased and reprogrammed providing for easy prototyping. Once a device is programmed the security bit can be used to provide protection from copying a proprietary design.

 

 

Applications:

 

  • Lattice/Vantis Programmable Array Logic(PAL) architecture
  • Electrically-erasable CMOS technology providing half power(90mA) at high speed  (-15=15-ns Tpd     -25=25-ns TPD)
  • Sixteen macrocells with configurable I/O architecture
  • Registered or combinatorial operation
  • Registers programmable as D.T.J-K. or S-R
  • Asynchronous clocking via product term or bank register clocking from external pins
  • Register preload for initialization
  • Space-saving 24-pin SKINNYDIP and 28-pin PLCC packages
  • Fully tested for 100% programming yield and high reliability
  • Extensive third-party software and programmer support through Fusion PLD partners

 

 

Specifications:

 

part no.

PALCE610H-25PC

Manufacturer

Lattice Semiconductor

supply ability

10000

datecode

10+

package

24PIN--DIP

remark

new and original stock

 

 

Competitive Advantage:

 

Warranty :180 days !
Free shipping: Order over $1000 win a free shipment fee
(goods weight below 3Kg) ,during 20130901-20130930 .


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