Although TSMC's 3nm chips have been mass-produced, as of yesterday, we have not seen chip companies release related products. Today, this situation has finally been broken.
U.S. chip company Marvell said it has officially released a data center chip based on TSMC's 3-nanometer (3nm) process. According to Marvell, the company's industry-first silicon building blocks in this node include 112G XSR SerDes (serializer/deserializer), Long Reach SerDes, PCIe Gen 6 / CXL 3.0 SerDes and 240 Tbps parallel chip-to-chip interconnect .
According to Marvell, SerDes and parallel interconnects act as high-speed lanes in the chip for exchanging data between chips or silicon components inside the chiplet. Together with 2.5D and 3D packaging, these technologies will remove system-level bottlenecks to advance the most complex semiconductor designs. SerDes also help reduce costs by reducing pins, traces, and board space. A rack in a hyperscale data center may contain tens of thousands of SerDes links.
According to their figures, the new parallel die-to-die interconnect enables aggregate data transfers of up to 240 Tbps, which is 45 percent faster than available alternatives for multi-die packaging applications. In other words, the interconnect transfer rate is equivalent to downloading 10,000 high-definition movies per second, despite distances of only a few millimeters or less.
Marvell integrates its SerDes and interconnect technologies into its flagship silicon solutions, including Teralynx switches_, PAM4 and coherent DSPs, Alaska Ethernet physical layer (PHY) devices, OCTEON processors_, Bravera memory controllers, Brightlane automotive Ethernet network chipsets and custom ASICs. And moving to a 3nm process allows engineers to reduce the cost and power consumption of chips and computing systems while maintaining signal integrity and performance.
3nm, a new milestone for TSMC
According to TSMC, the company's 3-nanometer (N3) process technology will be another full-generation process after the 5-nanometer (N5) process technology. When the N3 process technology is launched, it will be the most advanced process technology in the industry. Excellent PPA and transistor technology. Compared with N5 process technology, the logic density of N3 process technology will increase by about 70%, and the speed will increase by 10-15% at the same power consumption, or the power consumption will be reduced by 25-30% at the same speed.
However, N3 has a relatively narrow process window (the range of parameters that yield defined results) and may not be suitable for all applications in terms of throughput. Also, as manufacturing processes become more complex, their wayfinding, research and development times get longer, so we no longer see TSMC and other foundries popping up a whole new node every two years. For N3, TSMC’s new node introduction cycle will be extended to about 2.5 years. That means TSMC will need to offer an enhanced version of N3 to meet the needs of its customers, who are still looking for performance-per-watt improvements and transistor density increases every year or so.
At the 2022 Tech Symposium, TSMC also discussed four N3-derived manufacturing processes (a total of five 3nm-level nodes)—N3E, N3P, N3S, and N3X—that will be launched in the next few years. These N3 variants are designed to provide an improved process window, higher performance, higher transistor density and enhanced voltage for ultra-high performance applications.
Among them, N3E improves performance, reduces power consumption, and increases the process window, thereby improving brightness. But at the cost of slightly lower logic density at that node. Compared with N5, N3E will reduce power consumption by 34% (at the same speed and complexity) or improve performance by 18% (at the same power and complexity), and increase logic transistor density by 1.6 times.
According to reports, TSMC will launch N3P (a performance-enhanced version of its manufacturing process) as well as N3S (a density-enhanced version of the node) sometime around 2024. But TSMC has not revealed more information about these variants at this time. For those customers who require ultra-high performance regardless of power consumption and cost, TSMC will offer N3X, which is essentially the ideological successor of N4X. Again, TSMC didn't reveal details about the node other than to say it will support high drive currents and voltages.
It’s worth mentioning that all of TSMC’s technologies will support FinFlex, a TSMC “secret sauce” feature that greatly increases design flexibility and allows chip designers to precisely optimize performance, power consumption, and cost. In short, FinFlex allows chip designers to precisely tailor their building blocks to achieve higher performance, higher density and lower power consumption.
In practice, TSMC's FinFlex technology will allow chip designers to mix and match different types of standard cells within a block to precisely tailor performance, power consumption and area. For complex structures like CPU cores, this optimization provides many opportunities to increase core performance while still optimizing die size.
However, we must emphasize that FinFlex is not a substitute for node specialization (performance, density, voltage) as process technologies have greater variance in libraries or transistor structures than within a single process technology, but FinFlex appears to be the best way to optimize performance, power And a good way to cost TSMC's N3 node. Ultimately, this technology will bring the flexibility of FinFET-based nodes closer to that of nanosheet/GAAFET-based nodes, which will offer adjustable channel widths for higher performance or lower power consumption.