The parallel computing capacity of the GPU is very capable, but it also has disadvantages, that is, high power consumption, large volume, and expensive price.
After entering the 21st century, the needs of computing power showed two significant trends: First, the use of computing power used to be subdivided; second, users' requirements for computing power performance are getting higher and higher. GM's computing power chips can no longer meet the needs of users.
As a result, more and more companies have begun to strengthen the research and investment of special computing chips. The ASIC (Application Specific Integrated Circuit, a special integrated circuit) is a chip dedicated to specific tasks.
The official definition of ASIC refers to an integrated circuit specially designed and manufactured by the requirements of a specific user or the needs of a specific electronic system.
ASIC started in the 1970s and 80s. In the early days, it was used for computers. Later, it was mainly used for embedded control. In recent years, as mentioned earlier, it has begun to rise and used for AI reasoning, high -speed search, and visual and image processing.
Speaking of ASIC, we have to mention Google's famous TPU.
TPU, the full name of Tensor Processing Unit, tensor processing unit. The so -called "tensor" is a mathematical entity containing multiple numbers (multidimensional arrays).
At present, almost all machine learning systems use tensor as the basic data structure. Therefore, we can simply understand the "AI processing unit".
In 2015, in order to better complete your deep learning tasks and improve AI computing power, Google launched a chip specially used for neural network training, which is TPU V1.
Compared with traditional CPUs and GPUs, TPU V1 can get 15-30 times performance improvement in neural network computing, and the energy efficiency improvement has reached 30 to 80 times, which has brought great shocks to the industry.
In 2017 and 2018, Google continued to work hard to launch a stronger TPU V2 and TPU V3 for AI training and reasoning. In 2021, they launched the TPU V4, using 7nm process, the number of transistors reached 22 billion, the performance was 10 times compared to the previous generation, and 1.7 times stronger than the A hero of A100.
In addition to Google, there are many large manufacturers in recent years.
Intel acquired the Israeli AI chip company Habana Labs at the end of 2019. In 2022, the GAUDI 2 ASIC chip was released.
IBM Research Institute, at the end of 2022, released AI ASIC chip AIU.
Samsung also had ASIC a few years ago. At that time, it was a special chip of mining machines. That's right, many people know ASIC, starting with Bitcoin mining. Compared with the GPU and CPU mining, ASIC mining machines are more efficient and lower energy consumption.
ASIC mining machine
In addition to TPUs and mining machines, the other two types of well -known ASIC chips are DPUs and NPUs.
DPU is the data processing unit (Data Processing Unit), which is mainly used for data centers. Xiao Zaojun has previously introduced it. You can see here: What is the DPU of the whole network?
NPU is called Neural Processing Unit, which simulates human neurons and synapses in the circuit layer, and process data with deep learning instruction sets.
NPU is specially used for neural network reasoning, which can achieve efficient convolution and pooling operations. In some mobile phone chips, this thing is often integrated.
When it comes to mobile phone chips, it is worth mentioning that our mobile phone's current main chip, which is often referred to as the SOC chip, is actually an ASIC chip.
As a special customized chip, ASIC is the advantage? It's just an enterprise exclusive, dedicated logo and naming?
no.
Customization is the body tailoring. Based on the special tasks of the chip, the computing power and computing efficiency of the chip are strictly matched with the task algorithm. The core quantity of chips, the proportion of logic calculation units and control units, and cache, the entire chip architecture is also precisely customized.
Therefore, customized special chips can achieve extreme volume and power consumption. The reliability, confidentiality, computing power, and energy efficiency of such chips will be stronger than universal chips (CPUs, GPUs).
Everyone will find that the ASIC companies we mentioned earlier are large factories such as Google, Intel, IBM, and Samsung.
This is because the customized design of the chip has high requirements on the level of research and development technology of a company, and it costs greatly.
To make an ASIC chip, you must first go through complicated design processes such as code design, comprehensive, and back -end. After several months of production processing and packaging testing, you can get the chip to build the system.
Everyone has heard of "tape-out". Like the assembly line, the chip is manufactured through a series of process steps, which is the flow. Simply put, it is trial production.
ASIC's R & D process requires flow. The 14nm process, the streaming film takes about $ 3 million at a time. The 5nm process is as high as 47.25 million US dollars.
Once the flow fails, all the money is drifting, and a lot of time and energy are delayed. General small companies can't afford it at all.
So, is it unable to make a chip customization?
of course not. Next, it was another artifact to appear, that is -FPGA.
2.fpga (on -site programming door array)
FPGA, full English name Field Programmable Gate Array, on -site programming door array. FPGA has been very popular in the industry over the years, and its momentum is fiercer than ASIC, and it is even known as "universal chip".
In fact, simply, FPGA is a chip that can be reconstructed. It can make unlimited number of repeated programming after manufacturing to achieve the digital logic functions they want.
The reason why FPGA can achieve DIY is because of its unique structure.
FPGA by Configurable Logic Blocks，CLB、I/O Blocks，IOB、Programmable Interconnect Resources，PIR wait three programmable circuits, as well as static memory SRAM together.
CLB is the most important part of FPGA. It is the basic unit for realizing logical functions and carries the main circuit functions.
They are usually arranged into a array (logic unit array, LCA, Logic Cell array) and scattered throughout the chip.
IOB mainly completes the interface of logic on the chip and external pins, usually arranged around the chip.
PIR provides rich connection resources, including vertical mesh connection, programmable switch matrix, and programmable connection point. They realize the connection and constitute a circuit with specific functions.
Static memory SRAM, used to store programming data from internal IOB, CLB, and PIR, and form control of them, thereby completing system logic functions.
The CLB itself is mainly composed of the search table (LOOK-up Table, LUT), multiplexer, and Flip-Flop. They are used to carry the logical "door" in the loading circuit, which can be used to achieve complex logical functions.
In simple terms, we can understand LUT as RAM that stored the calculation results. When the user describes a logical circuit, the software will calculate the possible results and write this RAM. Each signal for logical operation is equivalent to entering a address to check the table. LUT will find the content corresponding to the address and return the result.
This "hardware" computing method obviously has a faster operation speed.
When the user uses FPGA, it can be designed by the hardware description language (Verilog or VHDL), and then the complete circuit design, and then the FPGA is "programmed" (burn) to load the design to the FPGA to achieve the corresponding functions.
During the power increase, the FPGA reads the data in the EPROM (scratching programming only memory) into the SRAM. After the configuration is completed, the FPGA enters the working state. After the power was dropped, the FPGA was restored into a white film, and the internal logic relationship disappeared. Repeatedly, the "live" customization is implemented.
FPGA's function is very powerful. Theoretically, if the scale of the door circuits provided by FPGA is large enough, it can achieve any logic function of any ASIC through programming.
FPGA is a product developed on the basis of PAL (programmable array logic), GAL (universal array logic) and other programmable devices. It belongs to a semi -customized circuit.
It was born in 1985 and the inventor was Xilinx (Sailing Si). Later, companies such as Altera, Lattice, Microsemi (MGMI) also participated in the field of FPGA and eventually formed the pattern of the four giants.
In May 2015, Intel acquired Altera at a price of 16.7 billion US dollars, and later collected a PSG (programmable solution division) department.
In 2020, Intel's competitor AMD was unwilling to show weaknesses, and acquired Xilinx for $ 35 billion.
As a result, it became Xilinx (AMD), Intel, Lattice, and Microsemi Giants (do not change soup).
In 2021, the market share of these four companies was 51%, 29%, 7%, and 6%, respectively, adding up to 93%of the total global share.
Not long ago, in October 2023, Intel announced the plan to split the PSG department and operate independently.
In the words of domestic FPGA manufacturers, including Fudan Microelectronics, Ziguang Guowei, Anlu Technology, Dongtu Technology, Gaoyun Semiconductor, Jingwei Qili, Jingwei Ya Ge, Zhi Duo Crystal, and Voltic core. It looks like a lot, but in fact there is a large technology gap.
3. The difference betweenasic and FPGA
Next, we focus on the difference between ASIC and FPGA, as well as the difference between them and CPU and GPUs.
ASIC and FPGA are essentially chips. AISC is a full custom chip, which is written to death and cannot be changed. FPGA is a semi -customized chip with flexible functions and strong playability.
We can still explain the difference between the two through an example.
ASIC uses molds to make toys. It is more troublesome to open up mold opening in advance. Moreover, once the mold is opened, there is no way to modify it. If you want to make a new toy, you must re -open the mold.
And FPGA, like using Lego bricks to make toys. You can get started with it, take a little time, you can set it up. If you are not satisfied, or if you want to put new toys, you can remove it and make it again.
Many design tools of ASIC and FPGA are the same. In the design process, FPGA is not as complicated as ASIC, and has removed some manufacturing processes and additional design verification steps, probably only 50%-70%of the ASIC process. The biggest flow process, FPGA is not needed.
This means that developing ASIC may take a few months or even a year. FPGA only takes a few weeks or months.
It is said that FPGA does not need to be filled, so does it mean that the cost of FPGA must be lower than ASIC?
uncertain.
FPGA can be prefabricated and programmed in the laboratory or on -site, without the need for disposable engineering costs (NRE). However, as a "general toy", its cost is 10 times that of ASIC. If the production volume is relatively low, then the FPGA will be cheaper. If the production volume is high, ASIC's disposable engineering costs are waded, then ASIC is cheap.
This is like the fee opening fee. The opening of the mold is very expensive, but if the sales volume is large, the mold opening will be cost -effective.
From the perspective of performance and power consumption, as a special customized chip, ASIC is stronger than FPGA.
FPGA is a general -edited chip with more redundant functions. No matter how you design it, there will be more components.
Xiao Zaojun also said that ASIC is customized, there is no waste, and the hard connection is used. Therefore, the performance is stronger and the power consumption is lower.
FPGA and ASIC are not simple competition and alternative relationships, but different positioning.
FPGA is now mostly used for product prototype development, design iterative, and specific applications of low output. It is suitable for products with short development cycles. FPGA is often used for ASIC verification.
ASIC is used to design chips with large scale, high complexity, or products with high maturity and large output.
FPGA is also particularly suitable for beginners to learn and participate in the competition. Many universities are now using FPGA to teach.
From the perspective of commercialization, the main application areas of FPGA are communication, defense, aviation, data centers, medical, automotive and consumer electronics.
FPGA used in the field of communication very early. Many base stations processing chips (baseband processing, beam -shaped, antenna transceiver, etc.) are FPGA used. The encoding and protocol acceleration of the core network also uses it. The data center used to be used on DPU and other components.
Later, many technologies were mature and set, and communication equipment vendors began to replace with ASIC to reduce costs.
It is worth mentioning that in recent years, many popular Open Ran, in fact, many of them are calculated using the Intel CPU. The energy consumption of this scheme is far less than FPGA and ASIC. This is also one of the main reasons that including Huawei and other equipment vendors who are unwilling to follow up OPEN RAN.
The field of automobiles and industries is mainly to see the delay advantage of FPGA, so it will be used on ADAS (high -end driving assistance system) and servo motor drive.
FPGA for consumer electronics is because the product iteration is too fast. The development cycle of ASIC is too long. When you make things, you are cold.
4.fpga, ASIC, GPU, who is the most suitable AI chip?
From the perspective of theory and architecture, the performance and cost of ASIC and FPGA must be better than the CPU and GPU.
The CPU and GPU follow the structure of the von Noonam architecture. The instructions must go through steps such as storage, decoding, execution, etc. When sharing in the sharing, they must experience arbitration and cache.
FPGA and ASIC are not von Nomann architecture (Harvard architecture). Taking FPGA as an example, it is essentially a architecture without instructions and no need to share memory.
FPGA's logical unit function has been determined during programming, and it is a software algorithm with hardware. For the demand for preservation status, sending in FPGA stocks and film memory (Bram) belong to their respective control logic and do not require arbitration and cache.
From the perspective of the ALU computing unit, the GPU is higher than the CPU. Because FPGA has almost no control module, all modules are ALU computing units, which is higher than GPU.
Therefore, comprehensively, FPGA's computing speed will be faster than the GPU.
Look at the power consumption.
The power consumption of the GPU is famous, and the single piece can reach 250W, or even 450W (RTX4090). And FPGA generally only 30 ~ 50W.
This is mainly because of memory reading. The GPU's memory interface (GDDR5, HBM, HBM2) bandwidth is extremely high, which is about 4-5 times that of the FPGA traditional DDR interface. But as far as the chip itself is concerned, the energy consumed by DRAM is more than 100 times that of SRAM. The GPU frequently read the DRAM processing, which generates high power consumption.
In addition, the main frequency of FPGA (less than 500MHz) is lower than the CPU, GPU (1 ~ 3GHz), and will also make its own power consumption lower. FPGA's work frequency is low, mainly due to the limitations of wiring resources. Some lines are going to go far, the clock frequency is high, so it is too late.
Finally, look at the delay, GPU delay is higher than FPGA.
GPUs usually need to divide different training samples into "BATCH (batch)" of fixed size. In order to maximize the parallelity, several BATCH needs to be collected and then processed uniformly.
FPGA's architecture is not batches. Each process of completing a packet can be output immediately, and the delay is more advantageous.
Then, the problem is. The GPU is not as good as FPGA and ASIC here. Why is it still a big hit for AI calculations now?
It is very simple. Under the ultimate pursuit of computing power performance and scale, the entire industry does not care about any cost and power consumption at all.
With the long -term efforts of Nvidia, the core number and operating frequency of the GPU have been increasing, and the chip area is getting larger and larger, which is a hard rigid computing power. Power consumption is dependent on the process, and passive heat dissipation such as water cooling, but not fire.
In addition to hardware, Xiao Zaojun also mentioned that Nvidia is very layout in software and ecology. Their CUDA they tinked is a core competitiveness of the GPU. Based on CUDA, beginners can get started soon for GPU development. They have worked hard for many years and have formed a mass foundation.
In contrast, the development of FPGA and ASIC is still too complicated and not suitable for popularization.
In terms of interfaces, although the GPU interface is relatively single (mainly PCIE), there is no FPGA flexibility (FPGA's programming, enabling it to easily connect any standard and non -standard interface), but for the server, it is enough. Can be used on it.
In addition to FPGA, the reason why ASIC does not do the GPU on AI is very related to its high cost, long development cycle, and huge development risk. Now the AI algorithm is changing fast, and the development cycle of ASIC is terrible.
Based on the above reasons, the GPU has a good situation.
In AI training, GPU's computing power is strong and can greatly improve efficiency.
In AI reasoning, input is generally a single object (image), so it is required to be lower, and it does not need any parallel, so the computing power advantage of the GPU is not so obvious. Many companies will start using cheaper and more power -saving FPGAs or ASIC for calculation.
The same is true of other computing scenarios. Looking at the absolute performance of the power, the first choice GPU. If the performance requirements are not so high, you can consider FPGA or ASIC, which can save it.
5. Last words
The knowledge about CPU, GPU, FPGA, and ASIC is introduced here.
They are typical representatives of calculating chips. All the current computing power scenarios of human beings are basically responsible for them.
With the development of the times, computing chips also have a new trend. For example, different computing power chips are mixed and match to use each other advantages. We control this method, called heterogeneous calculation. In addition, there is a brain chip that IBM takes the lead, similar to the nerve synapses of the brain, the processing process of simulated human brain has also made breakthroughs, and the heat climbed.
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