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Programmable IC Chip XC95144XL-7CS144I - xilinx - XC9500XL High-Performance CPLD Family

Programmable IC Chip XC95144XL-7CS144I - xilinx - XC9500XL High-Performance CPLD Family

Programmable IC Chip XC95144XL-7CS144I - xilinx - XC9500XL High-Performance CPLD Family

Product Details:

Place of Origin: PHILIPPINE
Brand Name: xilinx
Certification: Lead free / RoHS Compliant
Model Number: XC95144XL-7CS144I

Payment & Shipping Terms:

Minimum Order Quantity: 50
Price: Contact for Sample
Packaging Details: Contact for Sample
Delivery Time: Within 3days
Payment Terms: T/T in advance, Paypal, Western Union
Supply Ability: 5000
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Detailed Product Description


Quick Detail:


XC9500XL High-Performance CPLD Family





Each XC9500XL device is a subsystem consisting of multiple Function Blocks (FBs) and I/O Blocks (IOBs) fully interconnected by the FastCONNECT II switch matrix. The IOB provides buffering for device inputs and outputs. Each FB provides programmable logic capability with extra wide 54inputs and 18 outputs. The FastCONNECT II switch matrix connects all FB outputs and input signals to the FB inputs. For each FB, up to 18 outputs (depending on package pin-count) and associated output enable signals drive directly to the IOBs.





• Optimized for high-performance 3.3V systems

- 5 ns pin-to-pin logic delays, with internal system frequency up to 208 MHz

- Small footprint packages including VQFPs, TQFPs and CSPs (Chip Scale Package)

- Pb-free available for all packages

- Lower power operation

- 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals

- 3.3V or 2.5V output capability

- Advanced 0.35 micron feature size CMOS FastFLASH technology

• Advanced system features

- In-system programmable

- Superior pin-locking and routability with FastCONNECT II switch matrix

- Extra wide 54-input Function Blocks

- Up to 90 product-terms per macrocell with individual product-term allocation

- Local clock inversion with three global and one product-term clocks

- Individual output enable per output pin with local inversion

- Input hysteresis on all user and boundary-scan pin inputs

- Bus-hold circuitry on all user pin inputs

- Supports hot-plugging capability

- Full IEEE Std 1149.1 boundary-scan (JTAG) support on all devices

• Four pin-compatible device densities

- 36 to 288 macrocells, with 800 to 6400 usable gates

• Fast concurrent programming

• Slew rate control on individual outputs

• Enhanced data security features

• Excellent quality and reliability

- 10,000 program/erase cycles endurance rating

- 20 year data retention

• Pin-compatible with 5V core XC9500 family in common package footprints





part no.




supply ability







new and original stock



Competitive Advantage:


Warranty :180 days !
Free shipping: Order over $1000 win a free shipment fee
(goods weight below 3Kg) ,during 20130901-20130930 .

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