Integrated Circuit Chip AN87C196CA - Intel Corporation - CHMOS 16-BIT MICROCONTROLLER

Quick Detail:

CHMOS 16-BIT MICROCONTROLLER

Description:

The 87C196LB is a high-performance 16-bit microcontroller with integrated support for the J1850 communication protocol. The 87C196LB is composed of a high-speed core with the following peripherals: an asynchronous/synchronous serial I/O port (8096 compatible) with a dedicated 16-bit baud-rate generator; an additional synchronous serial I/O port with full duplex master/slave transceivers; a six-channel A/D converter with sample and hold; a flexible timer/counter structure with prescaler, cascading, and quadrature capabilities; six modularized, multiplexed high-speed I/O for capture and compare (called event processor array) with 200 ns resolution and double buffered inputs; and a sophisticated prioritized interrupt structure with programmable peripheral transaction server (PTS). The clock doubler circuitry and oscillator output signal enable a 4 MHz resonator to achieve the same internal clock speed as a more costly 8 MHz resonator in previous applications.

This same circuitry can drive other devices where a separate resonator was required in the past. Another costsavings feature is the fact that the I/O ports are driven low at reset, avoiding the need for pull-up resistors.

Applications:

■ 20 MHz operation†

■ 24 Kbytes of on-chip OTPROM

■ 768 bytes of on-chip register RAM

■ Register-to-register architecture

■ Peripheral transaction server (PTS) with high-speed, microcoded interrupt service routines

■ Integrated, industry-standard J1850 communication protocol

■ Six-channel/10-bit A/D with sample and hold

■ High-speed event processor array

— Six capture/compare channels

— Two compare-only channels

— Two 16-bit software timers†

16 MHz standard; 20 MHz is speed premium

■ Full-duplex serial I/O port with dedicated baud-rate generator

■ Enhanced full-duplex, synchronous serial I/O port (SSIO)

■ Programmable 8- or 16-bit external bus

■ Optional clock doubler with programmable clock output signal

■ SFR register that indicates the source of the last reset

■ Design enhancements for EMI reduction

■ Oscillator failure detection circuitry

■ Watchdog timer (WDT)

■ –40° C to +125° C ambient temperature

■ 52-pin PLCC package

Specifications:

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