The RFIC design is very similar to the IC design of the IC design. It is usually a customized process, assisted by one or more EDA tools. Part of the accuracy of the RF IC design is that the parasitic effect and the packaging characteristics have a first -order impact on the performance of the RF circuit. Therefore, RF IC design is usually an iterative process, and the entire IC design process will use EM simulation, parasitic modeling and packaging modeling in large quantities.
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RF IC design also has performance requirements and restrictions on the "system budget" of key parameters, such as noise coefficient, power, phase noise, harmonic, linearity, etc. The budget was determined by the system -level design team that the team passed the budget restriction and performance requirements to the RF designer responsible for each module in the system map. These modules are further decomposed into topology and circuits. These topology and circuits experience the iteration of design, simulation, optimization and layout simulation by using EM simulation tools that can process IC.
Integrated circuit design restrictions
Because some passive devices (such as inductance and capacitors) are strictly limited by the wafer factory, RF IC designers usually have limited size and value control of these devices. This leads to greater uncertainty in the design, and may need to design and test new elements in the repeated process with foundries to generate components that meet the requirements of the RF circuit.
In some cases, RF designers may need to be moderated with other packaging dynamics that have nothing to do with casting to accurately predict the parasitic effects and final device performance in the final assembly. Many RFICs are delivered in the form of nude chips, and the lead bonds are directly connected to components or trays instead of typical IC packaging and PCB layout.
Electromagnetic simulation
Once the RF IC enters the physical layout stage, there are usually multiple electromagnetic simulation, circuit simulation and parasitic extraction iteration. These simulation involves at least IC packaging, but may also consider the external circuits of PCB and devices. The reason is that the RF circuit is very similar to the high -sensitivity simulation circuit, which will cause significant performance changes due to the nearby external circuits, electric fields/magnetic fields, temperature, electromagnetic signals and other environmental factors.
Even after the streaming film, before submitting the final design and starting RFIC production, testing, model enhancement and additional optimization are usually required.
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